This book provides a comprehensive coverage of System-on-Chip (SoC) post-silicon validation and debug challenges and state-of-the-art solutions with contributions from SoC designers, academic researchers as well as SoC verification experts.  The readers will get a clear understanding of the existing debug infrastructure and how they can be effectively utilized to verify and debug SoCs. 

In our day-to-day activities, we interact with a wide variety of computing systems. When we use desktops or laptops, we are aware of the fact that these systems are computing something for us. However, in many systems, the computing is embedded in them, such as cyber-physical systems and Internet-of-Things (IoT) devices. When we drive a car or fly in an airplane, many computing devices seamlessly work together to ensure a pleasant and safe journey. Similarly, when we perform any financial transaction or share personal details using a smartphone, embedded computing devices try to ensure the security and privacy of these transactions. Can we assume that these computing devices are correct by con- struction and therefore we can safely rely on them? A short answer is that no one can prove the absolute infallibility of today’s computing systems. This book pro- vides a clear insight into the fundamental challenges associated with validation and debug of computing systems. This book also provides effective solutions to address these challenges.

Most of these computing systems consist of software (application programs), firmware, and hardware. The brain behind these computing systems is called System-on-Chip (SoC). A typical SoC includes one or more processor cores, coprocessors, caches, memory, controllers, converters, peripherals, input/output devices, sensors, and so on. To understand why SoC validation is so challenging, let us consider one of the simplest components in a SoC—an adder. An adder adds two input values and produces the result. Typically, the input values are 64-bit integers. Therefore, to verify this adder, we have to simulate several trillions (2 64 ? 2 64 ) of test vectors. Clearly, it is infeasible to apply trillions of test vectors to verify an adder. If we cannot completely verify a simple adder, what is the hope that we can verify complex SoCs. During the design stage (before fabrication), pre-silicon validation techniques try to identify and fix functional errors as well as nonfunctional requirements.