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Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs

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As VLSI technology scales into nanometer regime, chip design engineering faces several challenges. One profound change in the chip design business is that engineers cannot realize the design precisely into the silicon chips. Chip performance, manufacture yield, and lifetime thereby cannot be determined accurately at the design stage accordingly. The main culprit here is that many chip parameters— such as oxide thickness due to chemical and mechanical polish (CMP) and impurity density from doping fluctuations—cannot be determined or estimated precisely and thus become unpredictable at device, circuit, and system levels, respectively. The so-called manufacturing process variations start to play an essential role, and their influence on the performance, yield, and reliability becomes significant. As a result, variation-aware design methodologies and computer-aided design (CAD) tools are widely believed to be the key to mitigate the unpredictability challenges for 45nm technologies and beyond. Variational characterization, modeling, and optimization, hence, have to be incorporated into each step of the design and verification processes to ensure reliable chips and profitable manufacture yields.

Since process variation and chip performance uncertainties have become more pronounced as technologies scale down into the nanometer regime, accurate and efficient modeling or characterization of variations from the device to the architecture level have  become imperative for the successful design of VLSI chips. This book provides readers with tools for variation-aware design methodologies and computer-aided design (CAD) of VLSI systems, in the presence of process variations at the nanometer scale. It presents the latest developments for modeling and analysis, with a focus on statistical interconnect modeling, statistical parasitic extractions, statistical full-chip leakage and dynamic power analysis considering spatial correlations, statistical analysis and modeling for large global interconnects and analog/mixed-signal circuits.  Provides readers with timely, systematic and comprehensive treatments of statistical modeling and analysis of VLSI systems with a focus on interconnects, on-chip power grids and clock networks, and analog/mixed-signal circuits;Helps chip designers understand the potential and limitations of their design tools, improving their design productivity;Presents analysis of each algorithm with practical applications in the context of real circuit design;Includes numerical examples for the quantitative analysis and evaluation of algorithms presented.  Provides readers with timely, systematic and comprehensive treatments of statistical modeling and analysis of VLSI systems with a focus on interconnects, on-chip power grids and clock networks, and analog/mixed-signal circuits;Helps chip designers understand the potential and limitations of their design tools, improving their design productivity;Presents analysis of each algorithm with practical applications in the context of real circuit design;Includes numerical examples for the quantitative analysis and evaluation of algorithms presented. 

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