Throughout the evolution of microelectronics industry, SoC designers
have always been struggling to improve their productivity in order to fully
exploit the growing number of transistors on a chip achievable by the silicon
The answer to this challenge has always been increasing the level of
abstraction used for the SoC implementation. From transistors to gates, and
from gates to RTL, the design productivity has been maintained high enough
to keep pace with and take advantage of the silicon technologies.
Unfortunately, RTL as the design entry point cannot handle the complexity
of 500 million-transistor SoCs designed with the CMOS90 process
Two major directions are contributing to bridge the gap between design
productivity and process capacity:
• Raise the level of abstraction to specify and model a SoC design.
• Adopt a different design paradigm, going from hardwired blocks to
partially or fully programmable solutions, as pioneered by Paulin et al1.
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